US 12,178,144 B2
Top electrode last scheme for memory cell to prevent metal redeposit
Chung-Yen Chou, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,067.
Application 17/371,468 is a division of application No. 16/197,526, filed on Nov. 21, 2018, granted, now 11,088,323, issued on Aug. 10, 2021.
Application 18/362,067 is a continuation of application No. 17/371,468, filed on Jul. 9, 2021, granted, now 11,800,818.
Claims priority of provisional application 62/724,698, filed on Aug. 30, 2018.
Prior Publication US 2023/0380304 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01)
CPC H10N 70/063 (2023.02) [H10B 63/30 (2023.02); H10N 70/021 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02); G11C 2213/52 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a memory cell disposed over a substrate and comprising a data storage layer between a top metal layer and a bottom metal layer;
an etch stop layer overlies the top metal layer;
an upper dielectric layer overlies the etch stop layer, wherein outer sidewalls of the etch stop layer, outer sidewalls of the upper dielectric layer, and outer sidewalls of the top metal layer are aligned; and
a top electrode overlying the memory cell, wherein the top electrode directly contacts inner sidewalls of the top metal layer, inner sidewalls of the etch stop layer, and inner sidewalls of the upper dielectric layer.