US 12,178,053 B2
Memory device and method of forming the same
Chao-I Wu, Zhubei (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jan. 4, 2024, as Appl. No. 18/404,103.
Application 17/882,845 is a division of application No. 17/123,925, filed on Dec. 16, 2020, granted, now 11,502,128, issued on Nov. 15, 2022.
Application 18/404,103 is a continuation of application No. 17/882,845, filed on Aug. 8, 2022, granted, now 11,895,849.
Claims priority of provisional application 63/040,778, filed on Jun. 18, 2020.
Prior Publication US 2024/0147738 A1, May 2, 2024
Int. Cl. H10B 63/00 (2023.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); H01L 23/522 (2006.01); H01L 29/78 (2006.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/34 (2023.02) [G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 23/5226 (2013.01); H01L 29/78391 (2014.09); H10N 70/061 (2023.02); H10N 70/253 (2023.02); H10N 70/8265 (2023.02); H10N 70/841 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising a first memory cell, wherein the first memory cell comprises:
a drain electrode;
a source electrode overlying and spaced from the drain electrode;
a gate electrode;
a channel layer separating the gate electrode from the drain electrode and the source electrode, wherein the channel layer is on a sidewall of the source electrode; and
a data storage layer separating the channel layer from the drain electrode.