CPC H10B 61/00 (2023.02) [G11C 11/161 (2013.01); H01F 41/307 (2013.01); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02); B82Y 25/00 (2013.01); H10B 61/22 (2023.02)] | 20 Claims |
1. A semiconductor device including a magnetic random access memory (MRAM) cell, comprising:
an MRAM cell structure disposed over a substrate, the MRAM cell structure including a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode;
a first insulating layer disposed over the MRAM cell structure;
a first interlayer dielectric (ILD) layer disposed over the first insulating layer;
a second ILD layer disposed over the first ILD layer; and
a conductive contact in contact with the top electrode,
wherein a side face of the conductive contact includes a lateral protrusion,
wherein the second ILD layer includes a first dielectric layer, a second dielectric layer on the first dielectric layer and a third dielectric layer on the second dielectric layer, and
wherein the lateral protrusion protrudes into the first dielectric layer.
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