CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02)] | 20 Claims |
1. A microelectronic device, comprising:
a lower deck and an upper deck, each comprising a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers;
a first array of pillars extending through the stack structure of the lower deck; and
a second array of pillars extending through the stack structure of the upper deck,
at least some of the pillars of one or more of the first array and the second array exhibiting a greater degree of bending away from a vertical orientation than at least some others of the pillars of the one or more of the first array and the second array,
the pillars of the first array aligning with the pillars of the second array along an interface between the lower deck and the upper deck.
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