US 12,177,988 B2
Wafer level bump stack for chip scale package
Sreenivasan K Koduri, Allen, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Jul. 13, 2021, as Appl. No. 17/374,946.
Application 17/374,946 is a continuation of application No. 16/588,220, filed on Sep. 30, 2019, granted, now 11,064,615.
Prior Publication US 2021/0345495 A1, Nov. 4, 2021
Int. Cl. H05K 3/34 (2006.01); H05K 1/02 (2006.01); H05K 3/28 (2006.01); H05K 3/38 (2006.01)
CPC H05K 3/3421 (2013.01) [H05K 1/0234 (2013.01); H05K 1/0269 (2013.01); H05K 3/284 (2013.01); H05K 3/3494 (2013.01); H05K 3/386 (2013.01); H05K 2201/068 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A microelectronic device, comprising:
a die having a terminal surface, die terminals at the terminal surface, and a back surface located opposite from the terminal surface;
an interface tile having a lamina structure with a die attach surface and an external surface located opposite from the die attach surface, the interface tile having interface leads at the die attach surface and having external leads at the external surface, the external leads being electrically coupled to the interface leads through the lamina structure;
interface bonds between the die and the interface tile, wherein the die terminals are electrically coupled to the interface leads through the interface bonds; wherein in the lamina structure includes a plurality of sub-lamine, each of the plurality of sub-lamina including a different coefficient of thermal expansion (CTE); and
a die coating only on the back surface and lateral surfaces of the die.