US 12,177,973 B2
Printed wiring board
Shoichiro Sakai, Osaka (JP); Junichi Motomura, Osaka (JP); Koji Nitta, Osaka (JP); Masashi Iwamoto, Koka (JP); Mitsutaka Tsubokura, Osaka (JP); Mari Sogabe, Osaka (JP); and Akira Tsuchiko, Osaka (JP)
Assigned to SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka (JP); and SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., Koka (JP)
Appl. No. 17/922,872
Filed by SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka (JP); and SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., Koka (JP)
PCT Filed May 20, 2020, PCT No. PCT/JP2020/020002
§ 371(c)(1), (2) Date Nov. 2, 2022,
PCT Pub. No. WO2021/234875, PCT Pub. Date Nov. 25, 2021.
Prior Publication US 2023/0164926 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H05K 1/09 (2006.01); H05K 1/11 (2006.01)
CPC H05K 1/09 (2013.01) [H05K 1/115 (2013.01); H05K 2201/0355 (2013.01); H05K 2201/09509 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A printed wiring board comprising:
a base layer having insulating properties;
a first conductive layer directly or indirectly stacked on a front surface of the base layer, and including a copper foil;
a second conductive layer directly or indirectly stacked on a back surface of the base layer, and including a copper foil;
a stacked body for a via hole, the stacked body being stacked on an inner periphery and a bottom of a connection hole that extends through the first conductive layer and the base layer in a thickness direction, and being configured to electrically connect the first conductive layer and the second conductive layer to each other,
wherein the stacked body for the via hole has an electroless copper plating layer that is stacked on the inner periphery and the bottom of the connection hole, and an electrolytic copper plating layer that is stacked on a surface of the electroless copper plating layer,
wherein each copper foil contains a copper crystal grain oriented in a (100) plane orientation, and an average crystal grain size of copper of each copper foil is 10 μm or greater,
wherein the electroless copper plating layer includes palladium, and
wherein a stacking amount of the palladium per unit area of a surface of each copper foil is 0.03 μg/cm2 to 0.15 μg/cm2, the surface of each copper foil facing the electroless copper plating layer.