US 12,177,370 B2
PUF generators based on SRAM bit cells
Cormac Michael O'Connell, Kanata (CA)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Apr. 27, 2021, as Appl. No. 17/242,112.
Application 17/242,112 is a continuation of application No. 16/125,535, filed on Sep. 7, 2018, granted, now 11,005,669.
Claims priority of provisional application 62/585,760, filed on Nov. 14, 2017.
Prior Publication US 2021/0250191 A1, Aug. 12, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); H04L 9/32 (2006.01)
CPC H04L 9/3278 (2013.01) [G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A physical unclonable function (PUF) generator comprising:
a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells have a first logical state; and
an authentication circuit, coupled to the PUF cell array, wherein the authentication circuit is configured to access and determine second logical states of bit cells in at least one row of the PUF cell array and based on the determined second logical states of the bit cells in the at least one row of the PUF cell array, to generate a PUF signature, wherein the authentication circuit comprises:
a PUF control circuit, coupled to the plurality of bit cells and configured to provide a first voltage, a VDD, and a word line (WL) pulse to the PUF cell; and
a timing control circuit configured to control a width of the WL pulse, start and end times of the WL pulse, and synchronization between pulses applied on the WL during a read or write operation.