US 12,176,812 B2
Slope compensation induced offset error cancellation in a peak or valley current mode switching voltage regulator
Kae Wong, Allen, TX (US); and Rida Assaad, Murphy, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 27, 2022, as Appl. No. 17/875,192.
Prior Publication US 2024/0039405 A1, Feb. 1, 2024
Int. Cl. H02M 3/158 (2006.01); H02M 1/00 (2006.01)
CPC H02M 3/158 (2013.01) [H02M 1/0009 (2021.05); H02M 1/0025 (2021.05)] 18 Claims
OG exemplary drawing
 
1. A voltage converter, comprising:
a first transistor having a first control terminal and a first current terminal;
a sense circuit coupled to the first current terminal;
a comparator having a comparator input and a comparator output, the comparator output coupled to the first control terminal;
an error amplifier having an error amplifier output, the error amplifier output coupled to the comparator input;
a slope compensation circuit coupled to at least one of the error amplifier output or the sense circuit;
an amplifier having an amplifier input, and an amplifier output;
a second transistor having a second control terminal and a second current terminal, the second control terminal coupled to the amplifier output; and
a capacitor having a terminal coupled to the second current terminal and to the amplifier input.