US 12,176,805 B2
Control architecture for ac-dc and dc-ac conversion capable of bidirectional active and reactive power processing
Khurram K. Afridi, Boulder, CO (US); Usama Anwar, Los Angeles, CA (US); Dragan Maksimovic, Boulder, CO (US); and Robert W. Erickson, Boulder, CO (US)
Assigned to THE REGENTS OF THE UNIVERSITY OF COLORADO, A BODY CORPORATE, Denver, CO (US)
Filed by The Regents of the University of Colorado, a body corporate, Denver, CO (US)
Filed on Mar. 21, 2018, as Appl. No. 15/927,918.
Claims priority of provisional application 62/474,466, filed on Mar. 21, 2017.
Prior Publication US 2018/0278181 A1, Sep. 27, 2018
Int. Cl. H02M 1/42 (2007.01); G05F 1/70 (2006.01); H02M 7/797 (2006.01)
CPC H02M 1/4233 (2013.01) [G05F 1/70 (2013.01); H02M 7/797 (2013.01)] 11 Claims
OG exemplary drawing
 
11. A single-phase ac/dc bi-directional power converter comprising:
a single-phase converter stage, wherein the single-phase converter stage comprises a bridgeless boost topology; and
a controller comprising a compensator, wherein the controller comprises a duty cycle generation block and the controller is configured to:
receive an unrectified sensed ac voltage and an unrectified sensed ac current from the single-phase converter stage, scale one of the unrectified sensed ac voltage and the unrectified sensed ac current to generate a reference,
determine a difference between the other one of the unrectified sensed ac voltage and the unrectified sensed ac current and the reference to generate an error signal,
provide the error signal to the compensator, and
generate a duty cycle command for the single-phase converter stage based at least in part on an output of the compensator;
wherein:
the duty cycle generation block is configured such that an output of the compensator is sent to a first block and a second block, in the first block the output of the compensator is compared with zero to generate a binary duty cycle signal for a first leg of the bridgeless boost topology and in the second block the output of the compensator is directly sent if a duty cycle of first leg is 0 or is added to an amplitude of a ramp voltage and a sum is sent if the duty cycle of first leg is 1 to a second saturation block, the output of the second saturation block is then compared with the ramp voltage to generate the duty cycle for a second leg of the bridgeless boost topology.