US 12,176,465 B2
Light-emitting device
Chao-Hsing Chen, Hsinchu (TW); Jia-Kuen Wang, Hsinchu (TW); Tzu-Yao Tseng, Hsinchu (TW); Bo-Jiun Hu, Hsinchu (TW); Tsung-Hsun Chiang, Hsinchu (TW); Wen-Hung Chuang, Hsinchu (TW); Kuan-Yi Lee, Hsinchu (TW); Yu-Ling Lin, Hsinchu (TW); Chien-Fu Shen, Hsinchu (TW); and Tsun-Kai Ko, Hsinchu (TW)
Assigned to EPISTAR CORPORATION, Hsinchu (TW)
Filed by EPISTAR CORPORATION, Hsinchu (TW)
Filed on Apr. 20, 2023, as Appl. No. 18/136,921.
Application 18/136,921 is a continuation of application No. 17/206,647, filed on Mar. 19, 2021, granted, now 11,658,269.
Application 17/206,647 is a continuation of application No. 16/891,670, filed on Jun. 3, 2020, granted, now 10,985,295, issued on Apr. 20, 2021.
Application 16/891,670 is a continuation of application No. 16/384,890, filed on Apr. 15, 2019, granted, now 10,680,138, issued on Jun. 9, 2020.
Application 16/384,890 is a continuation of application No. 15/948,738, filed on Apr. 9, 2018, granted, now 10,297,723, issued on May 21, 2019.
Application 15/948,738 is a continuation of application No. 15/858,534, filed on Dec. 29, 2017, granted, now 10,199,544, issued on Feb. 5, 2019.
Application 15/858,534 is a continuation of application No. 15/350,893, filed on Nov. 14, 2016, granted, now 9,893,241, issued on Feb. 13, 2018.
Claims priority of application No. 104137443 (TW), filed on Nov. 13, 2015.
Prior Publication US 2023/0261148 A1, Aug. 17, 2023
Int. Cl. H01L 33/46 (2010.01); H01L 33/38 (2010.01); H01L 33/40 (2010.01)
CPC H01L 33/46 (2013.01) [H01L 33/382 (2013.01); H01L 33/38 (2013.01); H01L 33/405 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A light-emitting device, comprising:
a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer;
a via penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer;
a first contact layer covering the via, electrically connected to the first semiconductor layer, and formed on the second semiconductor layer;
a second contact layer formed on the second semiconductor layer and electrically connected to the second semiconductor layer;
a first insulating layer comprising a first insulating layer first opening formed on the second semiconductor layer to expose the first contact layer;
a first pad on the semiconductor stack and covering the first insulating first opening; and
a second pad on the semiconductor stack and separated from the first pad with a distance to define a region between the first pad and the second pad on the semiconductor stack, wherein the first contact layer comprises a protrusion covering the via and the second contact layer comprises a recess surrounding the via.