US 12,176,435 B2
Method for forming fin field effect transistor (FinFET) device structure with conductive layer between gate and gate contact
Chao-Hsun Wang, Taoyuan (TW); Kuo-Yi Chao, Hsinchu (TW); Rueijer Lin, Hsinchu (TW); Chen-Yuan Kao, Zhudong Township, Hsinchu County (TW); and Mei-Yun Wang, Chu-Pei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 2, 2022, as Appl. No. 17/684,692.
Application 17/684,692 is a division of application No. 16/663,085, filed on Oct. 24, 2019, granted, now 11,271,112.
Application 16/663,085 is a division of application No. 15/821,994, filed on Nov. 24, 2017, granted, now 10,505,045, issued on Dec. 10, 2019.
Prior Publication US 2022/0271164 A1, Aug. 25, 2022
Int. Cl. H01L 27/088 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/7851 (2013.01) [H01L 21/76897 (2013.01); H01L 23/535 (2013.01); H01L 29/41791 (2013.01); H01L 29/456 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a fin field effect transistor (FinFET) device structure, comprising:
forming a gate dielectric layer over a fin structure;
forming a gate electrode layer over the gate dielectric layer;
forming a first dielectric layer formed over the gate dielectric layer;
forming a first conductive layer on the gate dielectric layer, wherein a bottom surface of the first conductive layer is in direct contact a top surface of the gate electrode layer, a sidewall of the first conductive layer is in direct contact the first dielectric layer and spaced apart from the gate dielectric layer; and
forming a barrier layer over the first conductive layer and in direct contact with the first dielectric layer, wherein the first conductive layer and the barrier layer are made of different materials.