US 12,176,433 B2
Polarization enhancement structure for enlarging memory window
Chih-Yu Chang, New Taipei (TW); Mauricio Manfrini, Zhubei (TW); Hung Wei Li, Hsinchu (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 30, 2023, as Appl. No. 18/325,176.
Application 18/325,176 is a division of application No. 17/218,680, filed on Mar. 31, 2021, granted, now 11,705,516.
Claims priority of provisional application 63/135,109, filed on Jan. 8, 2021.
Prior Publication US 2023/0299198 A1, Sep. 21, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 29/24 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/78391 (2014.09) [H01L 29/24 (2013.01); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/66969 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a ferroelectric structure having a first side and a second side;
a gate structure disposed along the first side of the ferroelectric structure;
an oxide semiconductor disposed along the second side of the ferroelectric structure and having a first semiconductor conductivity type;
a source region and a drain region disposed on the oxide semiconductor, wherein the gate structure is laterally between the source region and the drain region; and
a polarization enhancement structure arranged on the oxide semiconductor between the source region and the drain region and comprising a semiconductor material having a second semiconductor conductivity type that is different than the first semiconductor conductivity type, wherein the polarization enhancement structure is arranged along opposing sides of the source region and along opposing sides of the drain region.