US 12,176,415 B2
Device with a dummy fin contacting a gate isolation region
Shih-Yao Lin, New Taipei (TW); and Chih-Han Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 25, 2022, as Appl. No. 17/814,756.
Application 17/814,756 is a division of application No. 16/939,943, filed on Jul. 27, 2020, granted, now 11,837,649.
Claims priority of provisional application 63/013,105, filed on Apr. 21, 2020.
Prior Publication US 2022/0359721 A1, Nov. 10, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 21/823462 (2013.01); H01L 21/823481 (2013.01); H01L 29/517 (2013.01); H01L 29/6656 (2013.01); H01L 29/6681 (2013.01); H01L 29/66818 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a dummy fin comprising a first portion and a second portion, wherein the dummy fin comprises a dielectric material;
a gate isolation region over and contacting the dummy fin;
a first gate stack and a second gate stack on opposing sides of, and contacting, the first portion of the dummy fin;
a contact etch stop layer on opposing sidewalls and a top surface of the second portion of the dummy fin;
a dummy gate dielectric between and contacting the contact etch stop layer and the second portion of the dummy fin; and
an inter-layer dielectric over the contact etch stop layer.
 
8. A device comprising:
a semiconductor substrate;
isolation regions extending into the semiconductor substrate;
a first protruding semiconductor fin and a second protruding semiconductor fin parallel to each other and protruding higher than the isolation regions;
a dummy fin between the first protruding semiconductor fin and the second protruding semiconductor fin, wherein the dummy fin comprises a first portion and a second portion;
a dummy gate dielectric contacting a sidewall and a top surface of the second portion of the dummy fin, wherein the first portion of the dummy fin is free from the dummy gate dielectric thereon;
a contact etch stop layer on the dummy gate dielectric;
a first gate stack and a second gate stack extending on top surfaces and sidewalls of the first protruding semiconductor fin and the second protruding semiconductor fin, respectively; and
a gate isolation region between the first gate stack and the second gate stack, wherein the gate isolation region is over and contacting the first portion of the dummy fin.
 
17. A device comprising:
a semiconductor substrate;
isolation regions extending into the semiconductor substrate;
a protruding semiconductor fin protruding higher than the isolation regions;
a dummy fin protruding higher than the isolation regions, wherein the dummy fin is parallel to the protruding semiconductor fin, and wherein the dummy fin comprises a first portion and a second portion;
a gate isolation region over and contacting the first portion of the dummy fin;
a gate stack contacting sidewalls of both of the dummy fin and the gate isolation region;
a dummy gate dielectric on sidewalls and a top surface of the second portion of the dummy fin;
a contact etch stop layer over the dummy gate dielectric; and
an inter-layer dielectric over the contact etch stop layer.