US 12,176,410 B2
Integrated logic and passive device structure
Chung-Liang Cheng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 31, 2021, as Appl. No. 17/463,402.
Prior Publication US 2023/0065446 A1, Mar. 2, 2023
Int. Cl. H01L 29/423 (2006.01); H01L 27/12 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 27/124 (2013.01); H01L 27/1251 (2013.01); H01L 27/1255 (2013.01); H01L 27/1266 (2013.01); H01L 27/127 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a logic component on a substrate, the logic component including a gate-all-around transistor and a thin film transistor vertically stacked on the gate-all-around transistor;
a passive component on the substrate, the logic component being disposed between the substrate and the passive component, the passive component including a metal-insulator-metal (MIM) structure; and
a via electrically connecting the logic component to the passive component,
wherein the gate-all-around transistor and the thin film transistor are vertically adjacent to each other without any MIM structure therebetween, and
wherein the gate-all-around transistor includes a multi-layer stack including a plurality of semiconductor lavers.