| CPC H01L 29/42376 (2013.01) [H01L 21/28114 (2013.01); H01L 21/28123 (2013.01); H01L 21/28518 (2013.01); H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/4238 (2013.01); H01L 29/45 (2013.01); H01L 29/4933 (2013.01); H01L 29/4983 (2013.01); H01L 29/66492 (2013.01); H01L 29/665 (2013.01); H01L 29/6659 (2013.01); H01L 29/7833 (2013.01)] | 20 Claims |
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1. A method of forming a transistor device, comprising:
forming an isolation structure in a semiconductor substrate enclosing a device region;
forming a device doping well in the device region;
forming a gate structure overlying the device region and the isolation structure, wherein the gate structure separates the device doping well along a first direction and comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction;
forming a pair of source/drain regions in the device region on opposite sides of the gate structure;
forming a sidewall spacer extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure; and
forming a resistive protection layer conformally covering top and sidewall surfaces of the sidewall spacer within the pair of recess regions.
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11. A method of forming a transistor device, comprising:
forming an isolation structure in a semiconductor substrate surrounding a device region;
forming a gate structure on the device region with a gate dielectric layer separating a gate electrode from the device region, wherein the gate structure is formed with a pair of recess regions respectively overly an interface region of the isolation structure and the device region, wherein the gate electrode forms an ‘H’ shape when viewed on a face of the gate structure; and
forming a sidewall spacer outlining the ‘H’ shape, extending from the isolation structure up to a top surface that is flush with a top surface of the gate structure; and
forming a pair of source/drain regions in the device region on opposite sides of the gate structure and laterally spaced apart by a channel region, wherein the channel region has a channel length extending along a first direction from one of the pair of source/drain regions to the other one of the pair of source/drain regions, wherein the channel region has a channel width extending along a second direction perpendicular to the first direction from one of the pair of recess regions to the other one of the pair of recess regions; and
forming a resistive protection layer within the pair of recess regions and extending conformally to cover a portion of a top surface of the gate electrode while leaving a remaining portion of the top surface of the gate electrode uncovered by the resistive protection layer.
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19. A method for manufacturing a transistor device, the method comprising:
forming an isolation structure in a semiconductor substrate, wherein the isolation structure demarcates a device region of the semiconductor substrate;
forming a gate structure overlying the device region of the semiconductor substrate, wherein the gate structure is formed with a pair of recess regions overlying an interface region of the isolation structure and the device region;
performing a doping process to the device region of the semiconductor substrate with the gate structure in place to form a pair of source/drain regions in the device region;
forming a sidewall spacer extending along sidewalls of the gate structure; and
conformally forming a resistive protection layer within the pair of recess regions, extending upwardly along a sidewall of the sidewall spacer, and further extending laterally along top surfaces of the sidewall spacer and the gate structure.
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