US 12,176,392 B2
Semiconductor device with silicide gate fill structure
Chung-Liang Cheng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 5, 2021, as Appl. No. 17/193,547.
Claims priority of provisional application 63/044,276, filed on Jun. 25, 2020.
Prior Publication US 2021/0408235 A1, Dec. 30, 2021
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/0673 (2013.01) [H01L 21/82345 (2013.01); H01L 27/088 (2013.01); H01L 29/42392 (2013.01); H01L 29/4966 (2013.01); H01L 29/4975 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
an interlevel dielectric layer;
a first transistor including:
a plurality of semiconductor nanosheets corresponding to channels of the first transistor;
a first trench formed in the interlevel dielectric layer;
a first gate dielectric positioned on a bottom of the first trench and on sidewalls of the first trench; and
a first gate electrode, including:
a first gate metal having a first material positioned in direct physical contact with a first portion of a sidewall of the first gate dielectric in the first trench;
a second gate metal having a second material positioned on the first gate metal and in direct physical contact with a second portion of the sidewall of the first gate dielectric in the first trench above the first portion of the sidewall of the first gate dielectric, wherein the second material is different than the first material;
a third gate metal positioned on the second gate metal and in direct physical contact with a third portion of the sidewall of the first gate dielectric in the first trench above the second portion of the sidewall of the first gate dielectric, the second gate metal being positioned between the first gate metal and the third gate metal, wherein the first gate metal, the second gate metal, and the third gate metal surround the semiconductor nanosheets;
first silicide positioned in the first trench above the first gate metal; and
a first conductive gate fill material positioned over the first gate metal and first silicide in the first trench, wherein the first conductive gate fill material extends to a higher vertical level within the first trench than the first gate metal, wherein the third gate metal, the first conductive gate fill material, the first silicide, and the first gate dielectric extend to a same vertical height within the first trench, a highest surface of the first gate metal is below a lowest surface of the first silicide in the first trench, wherein a highest surface of the second gate metal is below a lowest surface of the first silicide in the first trench.