US 12,176,391 B2
Semiconductor device structure having an isolation layer to isolate a conductive feature and a gate electrode layer
Lung-Kun Chu, New Taipei (TW); Mao-Lin Huang, Hsinchu (TW); Chung-Wei Hsu, Hsinchu (TW); Jia-Ni Yu, New Taipei (TW); Kuan-Lun Cheng, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 24, 2023, as Appl. No. 18/225,160.
Application 18/225,160 is a division of application No. 17/459,379, filed on Aug. 27, 2021, granted, now 11,756,995.
Prior Publication US 2023/0369393 A1, Nov. 16, 2023
Int. Cl. H01L 29/06 (2006.01); B82Y 10/00 (2011.01); H01L 21/768 (2006.01); H01L 21/822 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0665 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823481 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
first and second dielectric features;
a first semiconductor layer disposed between the first and second dielectric features, wherein the first semiconductor layer has a first surface and a second surface opposite the first surface;
an isolation layer disposed between the first and second dielectric features, wherein the isolation layer is in contact with the first and second dielectric features, and the first semiconductor layer is disposed over the isolation layer;
a gate dielectric layer disposed over the isolation layer;
a gate electrode layer disposed over the gate dielectric layer, wherein the gate electrode layer has an end extending to a level between a first plane defined by the first surface of the first semiconductor layer and a second plane defined by the second surface of the first semiconductor layer; and
first and second source/drain epitaxial features disposed between the first and second dielectric features, wherein the first source/drain epitaxial feature is disposed over the first semiconductor layer, the first surface of the first semiconductor layer faces the first source/drain epitaxial feature, and the second surface of the first semiconductor layer faces the isolation layer.