US 12,176,390 B2
Semiconductor device structure and method for forming the semiconductor device structure
Chun-Fai Cheng, Tin Shui Wa (HK); Liang-Yi Chen, Taipei (TW); Chi-An Wang, Hsinchu (TW); Kuan-Chung Chen, Taipei (TW); and Chih-Wei Lee, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 23, 2022, as Appl. No. 17/678,511.
Prior Publication US 2023/0268390 A1, Aug. 24, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 31/072 (2012.01)
CPC H01L 29/0665 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device structure, comprising:
forming a fin structure with alternating stacked first semiconductor layers and second semiconductor layers over a substrate;
forming a fin isolation structure beside the fin structure;
forming a dummy gate structure across the fin structure;
forming a source/drain opening in the fin structure beside the dummy gate structure;
forming epitaxial structures in the source/drain opening;
removing the dummy gate structure and the first semiconductor layers to form a gate opening between the second semiconductor layers and between the second semiconductor layers and the fin isolation structure;
forming a dielectric layer in the gate opening surrounding the second semiconductor layers and over the sidewalls of the fin isolation structure;
forming a first work function layer in the gate opening surrounding the dielectric layer and over the sidewalls of the fin isolation structure; and
forming a gate electrode layer in the gate opening between the second semiconductor layers and the fin isolation structure.