US 12,176,347 B2
Input/output devices
Sung-Hsin Yang, Hsinchu (TW); Jung-Chi Jeng, Tainan (TW); and Ru-Shang Hsiao, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 10, 2023, as Appl. No. 18/349,486.
Application 18/349,486 is a division of application No. 17/025,802, filed on Sep. 18, 2020, granted, now 11,699,702.
Claims priority of provisional application 63/015,842, filed on Apr. 27, 2020.
Prior Publication US 2023/0352483 A1, Nov. 2, 2023
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 29/41791 (2013.01); H01L 29/6681 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming, over a substrate, a first active region in a first area of the substrate and a second active region in a second area of the substrate;
forming a first dummy gate stack over a channel region of the first active region and a second dummy gate stack over a channel region of the second active region;
depositing a first spacer material layer over the first dummy gate stack, a source/drain region of the first active region, the second dummy gate stack, and a source/drain region of the second active region;
depositing a second spacer material layer over the first spacer material layer while the first spacer material layer covers the source/drain region of the first active region and the source/drain region of the second active region;
etching back the second spacer material layer to expose the first spacer material layer over the source/drain region of the first active region and the source/drain region of the second active region;
selectively removing the second spacer material layer in the second area;
after the selectively removing, depositing a third spacer material layer over the first dummy gate stack and the second dummy gate stack; and
etching the first spacer material layer, the second spacer material layer, and the third spacer material layer to form a first gate spacer along sidewalls of the first dummy gate stack and a second gate spacer along sidewalls of the second dummy gate stack,
wherein the first spacer material layer, the second spacer material layer and the third spacer material layer are of different compositions.