US 12,176,344 B2
Methods of forming semiconductor structure
Hsien-Wei Chen, Hsinchu (TW); and Ming-Fa Chen, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 3, 2021, as Appl. No. 17/465,867.
Application 17/465,867 is a division of application No. 16/035,702, filed on Jul. 15, 2018, granted, now 11,114,433.
Prior Publication US 2021/0398973 A1, Dec. 23, 2021
Int. Cl. H01L 27/06 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01)
CPC H01L 27/0688 (2013.01) [H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 24/09 (2013.01); H01L 24/33 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02379 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, comprising:
forming an interconnect structure over a substrate;
forming a pad over the interconnect structure, wherein the pad is electrically connected to the interconnect structure;
after forming the pad, forming a bonding dielectric layer over the interconnect structure and the pad; and
forming a bonding metal layer in the bonding dielectric layer to electrically connect to the interconnect structure, wherein the bonding metal layer comprises a via plug and a metal feature formed over the via plug, a height of the metal feature is greater than or equal to a height of the via plug, wherein the bonding metal layer extends in a thickness direction of the pad and extends above a top surface of the pad and below a bottom surface of the pad.