US 12,176,301 B2
Package structure and method for forming the same
Po-Chen Lai, Hsinchu County (TW); Chin-Hua Wang, New Taipei (TW); Ming-Chih Yew, Hsinchu (TW); Li-Ling Liao, Hsinchu (TW); Tsung-Yen Lee, Changhua County (TW); Po-Yao Lin, Hsinchu County (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 5, 2023, as Appl. No. 18/328,913.
Application 18/328,913 is a continuation of application No. 17/350,293, filed on Jun. 17, 2021, granted, now 11,705,406.
Prior Publication US 2023/0326879 A1, Oct. 12, 2023
Int. Cl. H01L 21/683 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/16 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/16 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/08 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/3512 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a semiconductor die bonding on a first surface of a redistribution structure through first bonding elements;
a wall structure bonding on the first surface of the redistribution structure through second bonding elements, wherein the wall structure includes a plurality of partitions laterally arranged in a discontinuous ring, and the semiconductor die is located within the discontinuous ring; and
a substrate on a second surface of the redistribution structure through third bonding elements and in electrical connection with the semiconductor die, wherein:
the semiconductor die has a first sidewall, a second sidewall connected to the first sidewall, a third sidewall opposite to the first sidewall and connected to the second sidewall, and a fourth sidewall opposite to the second sidewall and connected to the first and third sidewalls,
a first partition in the plurality of partitions is located immediately adjacent to and spaced apart from the first sidewall of the semiconductor die by a first distance, a second partition in the plurality of partitions is located immediately adjacent to and spaced apart from the second sidewall of the semiconductor die by a second distance, a third partition in the plurality of partitions is located immediately adjacent to and spaced apart from the third sidewall of the semiconductor die by a third distance, and the first distance is equal to the second distance and the third distance, and
the first partition is located immediately adjacent to and spaced apart from the second partition by a fourth distance, the second partition is located immediately adjacent to and spaced apart from the third partition by a fifth distance, and the fourth distance is equal to the fifth distance.