US 12,176,298 B2
Floating die package
Benjamin Stassen Cook, Rockwall, TX (US); Steven Kummerl, Carrollton, TX (US); and Kurt Peter Wachtler, Richardson, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Dec. 8, 2020, as Appl. No. 17/115,734.
Application 17/115,734 is a continuation of application No. 15/248,151, filed on Aug. 26, 2016, granted, now 10,861,796.
Claims priority of provisional application 62/334,133, filed on May 10, 2016.
Prior Publication US 2021/0091012 A1, Mar. 25, 2021
Int. Cl. H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/4825 (2013.01); H01L 21/56 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/315 (2013.01); H01L 23/49513 (2013.01); H01L 23/4952 (2013.01); H01L 23/49541 (2013.01); H01L 23/49575 (2013.01); H01L 24/48 (2013.01); H01L 24/45 (2013.01); H01L 24/85 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/45014 (2013.01); H01L 2224/45015 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/45565 (2013.01); H01L 2224/45664 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/85203 (2013.01); H01L 2224/85205 (2013.01); H01L 2224/85207 (2013.01); H01L 2224/8592 (2013.01); H01L 2224/9205 (2013.01); H01L 2224/98 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/18165 (2013.01)] 27 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a substrate including first conductors and second conductors;
a first semiconductor die having opposite first and second surfaces, the first surface spaced apart from and facing towards the substrate;
first bond wires coupled between the second surface and the first conductors;
a second semiconductor die having opposite third and fourth surfaces, the third surface facing directly towards the second surface;
second bond wires coupled between the fourth surface and the second conductors; and
a molding structure covering at least respective portions of the substrate, the first and second bond wires, and the first and second semiconductor dies, in which the molding structure includes:
a cavity around at least portions of the first and second semiconductor dies, the cavity including a space between the first surface and the substrate; and
an opening extending through the molding structure and connecting directly with the cavity.