US 12,176,293 B2
Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration
Lars Liebmann, Mechanicsville, NY (US); Jeffrey Smith, Clifton Park, NY (US); Daniel Chanemougame, Niskayuna, NY (US); Paul Gutwin, Williston, VT (US); Brian Cline, Austin, TX (US); Xiaoqing Xu, Austin, TX (US); and David Pietromonaco, San Jose, CA (US)
Assigned to TOKYO ELECTRON LIMITED, Tokyo (JP)
Filed by TOKYO ELECTRON LIMITED, Tokyo (JP)
Filed on Dec. 3, 2021, as Appl. No. 17/541,561.
Claims priority of provisional application 63/121,605, filed on Dec. 4, 2020.
Prior Publication US 2022/0181263 A1, Jun. 9, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5383 (2013.01) [H01L 23/481 (2013.01); H01L 23/49833 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A multi-tier semiconductor structure, comprising:
a lower semiconductor device tier;
a lower signal wiring structure electrically connected to the lower semiconductor device tier;
a primary power delivery network (PDN) structure disposed over the lower semiconductor device tier and the lower signal wiring structure and electrically connected to the lower semiconductor device tier;
an upper semiconductor device tier disposed over and electrically connected to the primary PDN structure;
an upper signal wiring structure disposed over the primary PDN structure and electrically connected to the upper semiconductor device tier;
a secondary PDN structure disposed between the primary PDN structure and the lower semiconductor device tier and the lower signal wiring structure and electrically connecting the primary PDN structure to the lower semiconductor device tier, the secondary PDN structure being narrower than the primary PDN structure; and
a through-silicon via (TSV) structure that penetrates the primary PDN structure and the secondary PDN structure and directly electrically connects the lower semiconductor device tier to the upper semiconductor device tier.