US 12,176,286 B2
Memory device and method of forming the same
Li-Shyue Lai, Hsinchu Country (TW); Chien-Hao Huang, Hsinchu (TW); Chia-Yu Ling, Hsinchu (TW); Katherine H Chiang, New Taipei (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 11, 2022, as Appl. No. 17/669,382.
Claims priority of provisional application 63/230,073, filed on Aug. 6, 2021.
Prior Publication US 2023/0038958 A1, Feb. 9, 2023
Int. Cl. H10B 51/20 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 51/30 (2023.01)
CPC H01L 23/5283 (2013.01) [H01L 23/5226 (2013.01); H10B 51/20 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
an alternating stack of dielectric layers and word line layers comprising a staircase structure, and the staircase structure stepping downward from a first direction and comprising at least one turn;
pairs of bit lines and source lines spaced apart from one another and extending in a second direction that is perpendicular to the first direction;
a data storage layer covering a sidewall of the alternating stack; and
channel layers interposed between the data storage layer and the pairs of bit lines and source lines, wherein the pairs of bit lines and source lines are in lateral contact with the data storage layer through the channel layers.