US 12,176,285 B2
Transformer guard trace
Vijaylaxmi Gumaste Khanolkar, Pune (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Jan. 23, 2020, as Appl. No. 16/750,225.
Application 16/750,225 is a continuation in part of application No. 16/236,730, filed on Dec. 31, 2018, granted, now 11,482,477.
Claims priority of application No. 201941004011 (IN), filed on Feb. 1, 2019.
Prior Publication US 2020/0211961 A1, Jul. 2, 2020
Int. Cl. H01L 23/495 (2006.01); H01F 17/00 (2006.01); H01F 27/28 (2006.01); H01F 41/04 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H05K 3/46 (2006.01)
CPC H01L 23/5227 (2013.01) [H01F 17/0006 (2013.01); H01F 27/2804 (2013.01); H01F 27/288 (2013.01); H01F 41/041 (2013.01); H01L 23/495 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H05K 3/4611 (2013.01); H01L 2224/32188 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/1517 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A packaged electronic device, comprising:
first conductive leads along a first side of a package structure;
second conductive leads along a second side of the package structure;
a first semiconductor die attached to a first die attach pad;
a second semiconductor die attached to a second die attach pad;
a magnetic assembly attached to a support structure in the package structure, the magnetic assembly including:
a multilevel lamination structure, including: a first patterned conductive feature having multiple turns in a first level to form a first winding, a second patterned conductive feature having multiple turns in a different level to form a second winding, and a conductive guard trace spaced apart from and between the first patterned conductive feature and the second side of the package structure;
a first core structure attached to a first side of the multilevel lamination structure; and
a second core structure attached to a second side of the multilevel lamination structure;
a first set of electrical connections that couple the first semiconductor die, the first patterned conductive feature, and at least one of the first conductive leads in a first circuit; and
a second set of electrical connections that couple the second semiconductor die, the second patterned conductive feature, the conductive guard trace, and at least one of the second conductive leads in a second circuit isolated from the first circuit.