US 12,176,266 B2
Through-substrate via formation to enlarge electrochemical plating window
Hung-Ling Shih, Tainan (TW); Ming Chyi Liu, Hsinchu (TW); and Jiech-Fun Lu, Madou Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 4, 2022, as Appl. No. 17/880,854.
Application 17/880,854 is a division of application No. 17/150,048, filed on Jan. 15, 2021, granted, now 11,652,025.
Prior Publication US 2022/0375828 A1, Nov. 24, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 27/146 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76898 (2013.01); H01L 27/14636 (2013.01); H01L 27/1464 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip (IC), comprising:
a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate;
an insulating structure disposed along inner sidewalls of the semiconductor substrate, wherein the inner sidewalls of the semiconductor substrate extend through the semiconductor substrate;
a blocking layer disposed along inner sidewalls of the insulating structure, wherein a bottommost surface of the blocking layer is above a bottommost surface of the insulating structure and above a bottommost surface of the semiconductor substrate; and
a through-substrate via (TSV) comprising a first portion and a second portion, wherein the first portion extends along a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure, and wherein the second portion extends from the first portion to the conductive structure and has a maximum width less than that of the first portion.