US 12,176,257 B2
Semiconductor structure having an anti-arcing pattern disposed on a passivation layer
Sheng-An Kuo, Hsinchu (TW); Ching-Jung Yang, Taoyuan (TW); Hsien-Wei Chen, Hsinchu (TW); Jie Chen, New Taipei (TW); and Ming-Fa Chen, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 14, 2023, as Appl. No. 18/352,271.
Application 18/352,271 is a continuation of application No. 17/667,564, filed on Feb. 9, 2022, granted, now 11,769,704.
Application 17/667,564 is a continuation of application No. 16/877,508, filed on May 19, 2020, granted, now 11,251,100, issued on Feb. 15, 2022.
Claims priority of provisional application 62/905,426, filed on Sep. 25, 2019.
Prior Publication US 2023/0360986 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/3114 (2013.01) [H01L 21/561 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05099 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16145 (2013.01); H01L 2924/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure, comprising:
a first semiconductor die;
a second semiconductor die stacked over the first semiconductor die, and the second semiconductor die comprising pads;
a first bonding structure disposed between the first semiconductor die and the second semiconductor die;
a second bonding structure disposed between the first bonding structure and the second semiconductor die;
a first encapsulation portion laterally encapsulating the first semiconductor die and the first bonding structure;
a second encapsulation portion laterally encapsulating the second semiconductor die;
a passivation layer disposed over a top surface of the second semiconductor die and the second encapsulation portion;
an anti-arcing pattern disposed over the passivation layer;
a post passivation layer disposed over the passivation layer to cover a first portion of the anti-arcing pattern; and
conductive terminals over the second semiconductor die, wherein the conductive terminals are electrically connected to the pads of the second semiconductor die, wherein the first portion of the anti-arcing pattern is electrically insulated from the conductive terminals.