US 12,176,249 B2
3D nano sheet method using 2D material integrated with conductive oxide for high performance devices
H. Jim Fulford, Albany, NY (US); Mark I. Gardner, Albany, NY (US); and Partha Mukhopadhyay, Albany, NY (US)
Assigned to TOKYO ELECTRON LIMITED, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Feb. 8, 2022, as Appl. No. 17/667,390.
Prior Publication US 2023/0253261 A1, Aug. 10, 2023
Int. Cl. H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823821 (2013.01) [H01L 21/823814 (2013.01); H01L 27/0924 (2013.01); H01L 29/78696 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a stack of layers comprising:
a first layer of a semiconductive-behaving material; and
a second layer of the semiconductive-behaving material separated from the first layer of the semiconductive-behaving material by a dielectric material;
selectively forming a metal contact on both the first layer of the semiconductive-behaving material and the second layer of the semiconductive-behaving material;
forming a two-dimensional (2D) material on the first layer of the semiconductive-behaving material;
forming the 2D material on the second layer of the semiconductive-behaving material;
forming a high-k dielectric material on the 2D material on the first layer of the semiconductive-behaving material;
forming the high-k dielectric material on the 2D material on the second layer of the semiconductive-behaving material; and
forming a gate metal on the high-k dielectric material.