US 12,176,246 B2
Dielectric capping structure overlying a conductive structure to increase stability
Hsin-Yen Huang, New Taipei (TW); Chi-Lin Teng, Taichung (TW); Hai-Ching Chen, Hsinchu (TW); Shau-Lin Shue, Hsinchu (TW); Shao-Kuan Lee, Kaohsiung (TW); Cheng-Chin Lee, Taipei (TW); and Ting-Ya Lo, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 2, 2023, as Appl. No. 18/363,865.
Application 17/729,429 is a division of application No. 16/876,432, filed on May 18, 2020, granted, now 11,322,395, issued on May 3, 2022.
Application 18/363,865 is a continuation of application No. 17/729,429, filed on Apr. 26, 2022, granted, now 11,810,815.
Claims priority of provisional application 62/949,545, filed on Dec. 18, 2019.
Prior Publication US 2023/0377954 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 21/764 (2006.01); H01L 23/528 (2006.01)
CPC H01L 21/7682 (2013.01) [H01L 23/5329 (2013.01); H01L 21/02167 (2013.01); H01L 21/764 (2013.01); H01L 21/76834 (2013.01); H01L 23/528 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a conductive structure disposed within a dielectric structure;
a first dielectric layer overlying the dielectric structure;
a dielectric capping layer on the conductive structure, wherein opposing sidewalls of the dielectric capping layer are aligned with opposing sidewalls of the conductive structure; and
a second dielectric layer over the first dielectric layer and the dielectric capping layer, wherein the second dielectric layer directly contacts the opposing sidewalls of the dielectric capping layer, the opposing sidewalls of the conductive structure, and a top surface of the first dielectric layer.