CPC H01L 21/31053 (2013.01) [C09G 1/02 (2013.01); C09K 3/1409 (2013.01); C23F 1/12 (2013.01); H01L 21/02019 (2013.01); H01L 21/30625 (2013.01); H01L 21/3063 (2013.01); H01L 21/31055 (2013.01); H01L 21/31111 (2013.01)] | 20 Claims |
1. A method for manufacturing a semiconductor, comprising:
forming a metal oxide layer over a gate structure over a substrate;
forming a dielectric layer over the metal oxide layer;
forming a metal layer over the metal oxide layer; and
performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation comprises a ceria compound.
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