US 12,176,213 B2
Semiconductor structure and manufacturing method using different ion implantation energy
Yi Tang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jul. 28, 2022, as Appl. No. 17/815,623.
Claims priority of application No. 202210575586.9 (CN), filed on May 24, 2022.
Prior Publication US 2023/0386845 A1, Nov. 30, 2023
Int. Cl. H01L 21/265 (2006.01); H01L 21/768 (2006.01); H01L 21/822 (2006.01); H10B 12/00 (2023.01)
CPC H01L 21/2652 (2013.01) [H01L 21/7688 (2013.01); H01L 21/8221 (2013.01); H10B 12/482 (2023.02); H10B 12/488 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a word line region, a bit line region, and a capacitive region arranged adjacently, wherein the bit line region and the capacitive region are located on two opposite sides of the word line region;
forming a first stacked structure that covers a surface of the substrate, wherein the first stacked structure comprises a first sacrificial layer located on the surface of the substrate and a first semiconductor layer located on a surface of the first sacrificial layer;
forming a second stacked structure that covers a surface of the first stacked structure, wherein the second stacked structure comprises a second sacrificial layer located on the surface of the first stacked structure and a second semiconductor layer located on a surface of the second sacrificial layer; and
performing an ion implantation on the first semiconductor layer and the second semiconductor layer, wherein an energy at which the ion implantation is performed on the first semiconductor layer is greater than an energy at which the ion implantation is performed on the second semiconductor layer, to maintain a concentration of doped ions in the first semiconductor layer located in the bit line region and the capacitive region within a preset concentration range, and a concentration of doped ions in the second semiconductor layer located in the bit line region and the capacitive region within the preset concentration range.