US 12,176,209 B2
Formation of stacked lateral semiconductor devices and the resulting structures
Harry Luan, Saratoga, CA (US)
Assigned to TC Lab, Inc., Gilroy, CA (US)
Filed by TC Lab, Inc., Gilroy, CA (US)
Filed on Apr. 13, 2021, as Appl. No. 17/229,655.
Application 17/229,655 is a division of application No. 15/989,097, filed on May 24, 2018, granted, now 10,978,297.
Application 15/989,097 is a continuation in part of application No. 15/957,865, filed on Apr. 19, 2018, granted, now 10,748,903, issued on Aug. 18, 2020.
Prior Publication US 2021/0233767 A1, Jul. 29, 2021
Int. Cl. H01L 29/74 (2006.01); G11C 11/39 (2006.01); H01L 21/02 (2006.01); G11C 17/06 (2006.01)
CPC H01L 21/0259 (2013.01) [H01L 21/0257 (2013.01); H01L 29/7436 (2013.01); G11C 11/39 (2013.01); G11C 17/06 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A multi-layer semiconductor memory cell array, comprising:
a semiconductor substrate;
a first m by n array of semiconductor memory cells extending in a first x direction-y direction plane and electrically connected in a x direction to first terminal lines;
at least one second m by n array of the semiconductor memory cells extending in the a second x direction-y direction plane and electrically connected in the x direction to the first terminal lines, the at least one second m by n array of the semiconductor memory cells being stacked vertically above the first m by n array of the semiconductor memory cells; and
each of the semiconductor memory cells comprising only a single crystal silicon, and wherein m and n are integers.