US 12,176,063 B2
Computing-in-memory architecture
Yi-Chun Shih, Taipei (TW); Chia-Fu Lee, Hsinchu (TW); Yu-Der Chih, Hsinchu (TW); and Jonathan Tsung-Yung Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 10, 2022, as Appl. No. 17/884,650.
Application 17/884,650 is a continuation of application No. 17/337,889, filed on Jun. 3, 2021, granted, now 11,450,364.
Claims priority of provisional application 63/070,863, filed on Aug. 27, 2020.
Prior Publication US 2022/0415373 A1, Dec. 29, 2022
Int. Cl. G11C 7/12 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 16/04 (2006.01); G11C 16/30 (2006.01)
CPC G11C 7/12 (2013.01) [G11C 5/06 (2013.01); G11C 7/1045 (2013.01); G11C 7/1048 (2013.01); G11C 16/0433 (2013.01); G11C 16/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
a bit line; and
a plurality of computing cells connected to the bit line, each computing cell comprising:
a memory element having a data output terminal and configured to store a bit of data and to provide the bit of data at the data output terminal when data are read from the computing cells; and
a logic element having a first input terminal and a second input terminal, wherein the first input terminal is coupled to the data output terminal of the memory element and the second input terminal is configured to receive a select signal.