US 12,176,062 B2
Memory device
He-Zhou Wan, Shanghai (CN); Xiu-Li Yang, Shanghai (CN); Pei-Le Li, Nanjing (CN); and Ching-Wei Wu, Nantou County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); TSMC NANJING COMPANY LIMITED, Nanjing (CN); and TSMC CHINA COMPANY LIMITED, Shanghai (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); TSMC Nanjing Company Limited, Nanjing (CN); and TSMC China Company Limited, Shanghai (CN)
Filed on Jun. 16, 2023, as Appl. No. 18/336,428.
Application 18/336,428 is a continuation of application No. 17/853,401, filed on Jun. 29, 2022, granted, now 11,721,374.
Application 17/853,401 is a continuation of application No. 17/182,655, filed on Feb. 23, 2021, granted, now 11,393,509, issued on Jul. 19, 2022.
Claims priority of application No. 202110136033.9 (CN), filed on Feb. 1, 2021.
Prior Publication US 2023/0326501 A1, Oct. 12, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 5/14 (2006.01); G11C 7/12 (2006.01); G11C 8/10 (2006.01)
CPC G11C 7/109 (2013.01) [G11C 5/147 (2013.01); G11C 5/148 (2013.01); G11C 7/1057 (2013.01); G11C 7/1063 (2013.01); G11C 7/1069 (2013.01); G11C 7/1084 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); G11C 8/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array configured to operate according to a first global write signal;
a first latch configured to generate a first latch write data based on a clock signal; and
a first logic element configured to generate the first global write signal based on the clock signal and the first latch write data.