US 12,176,049 B2
MIM eFuse memory devices and fabrication method thereof
Meng-Sheng Chang, Chu-bei (TW); Chia-En Huang, Xinfeng Township (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,223.
Application 18/362,223 is a continuation of application No. 17/396,398, filed on Aug. 6, 2021, granted, now 11,756,640.
Prior Publication US 2023/0377666 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 17/00 (2006.01); G11C 17/16 (2006.01); H10B 20/20 (2023.01)
CPC G11C 17/165 (2013.01) [H10B 20/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of first interconnect structures disposed in a first metallization layer of a plurality of metallization layers over a substrate; and
a plurality of access transistors disposed over the first metallization layer and coupled to a plurality of fuse resistors, wherein each of the plurality of access transistors is formed as a back-gate transistor including a source terminal, a drain terminal, and a gate terminal that is disposed closer to the substrate than the source terminal and the drain terminal;
wherein each of the plurality of first interconnect structures is coupled to a corresponding one of the plurality of access transistors in series, operatively serving as a respective one of a plurality of one-time programmable electrical fuses.