CPC G11C 16/34 (2013.01) [G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] | 25 Claims |
1. An apparatus, comprising:
a substrate;
a plurality of plate lines parallel to the substrate;
a plurality of bit line pillars orthogonal to the substrate and connected with a bit line decoder;
a plurality of word line pillars orthogonal to the substrate and connected with a word line decoder; and
a plurality of memory cells each comprising a respective storage element and a respective selection element that comprises a first node, a second node, and a gate, wherein:
the first node is connected with the respective storage element, the second node is connected with a bit line pillar of the plurality of bit line pillars, and the gate is connected with a word line pillar of the plurality of word line pillars;
the respective storage element comprises a chalcogenide material, the chalcogenide material configured to store a logic state of a set of logic states based at least in part on a polarity of a first voltage applied to the chalcogenide material via the bit line pillar of the plurality of bit line pillars, the bit line pillar connected with a plate line of the plurality of plate lines; and
the respective selection element is connected with the respective storage element and configured to selectively connect the chalcogenide material with the bit line pillar of the plurality of bit line pillars based at least in part on a second voltage of the word line pillar of the plurality of word line pillars.
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