US 12,176,039 B2
Setting levels for a programming operation in a neural network array
Hieu Van Tran, San Jose, CA (US); Stanley Hong, San Jose, CA (US); Stephen Trinh, San Jose, CA (US); Thuan Vu, San Jose, CA (US); Steven Lemke, Boulder Creek, CA (US); Vipin Tiwari, Dublin, CA (US); and Nhan Do, Saratoga, CA (US)
Assigned to SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Apr. 27, 2023, as Appl. No. 18/140,103.
Application 18/140,103 is a division of application No. 17/082,956, filed on Oct. 28, 2020, granted, now 11,682,459.
Claims priority of provisional application 63/024,351, filed on May 13, 2020.
Prior Publication US 2023/0268004 A1, Aug. 24, 2023
Int. Cl. G11C 16/10 (2006.01); G06N 3/065 (2023.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/10 (2013.01) [G06N 3/065 (2023.01); G11C 11/5628 (2013.01); G11C 16/0425 (2013.01); G11C 16/0433 (2013.01); G11C 16/14 (2013.01); G11C 16/3459 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method comprising:
determining a program resolution current value; and
setting N current levels for a plurality of non-volatile memory cells in a neural network array, where the non-volatile memory cells respectively can be programmed to any of the N current levels, such that a delta current between adjacent current levels within the N current levels is a multiple of the program resolution current value;
wherein the delta current is at least a 1 sigma variation of one of the N current levels.