| CPC G11C 11/4096 (2013.01) | 19 Claims |
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1. A memory device comprising:
a memory array including a set of memory cells, each of the set of memory cells including a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line;
a first transistor including:
a source/drain electrode coupled to a controller, and
another source/drain electrode coupled to the bit line; and
a second transistor including a gate electrode coupled to the bit line, the second transistor to conduct current corresponding to data stored by a memory cell of the set of memory cells;
wherein the controller is to:
enable, during a programming phase, the first transistor and the corresponding transistor of the memory cell, and
apply, during the programming phase, a voltage corresponding to the data to the source/drain electrode of the first transistor.
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