| CPC G11C 11/161 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1659 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); H10B 61/20 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] | 20 Claims |
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1. A memory device, comprising:
a plurality of circuit layers disposed one above another, each circuit layer comprising one or more memory cell arrays;
a plurality of conductive through via structures penetrating though the circuit layers; and
a plurality of bitlines, each bitline comprising a plurality of bitline segments disposed on the circuit layers respectively, the bitline segments being electrically connected through one of the conductive through via structures, each bitline segment being coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed;
wherein the circuit layers comprise a first circuit layer and a second circuit layer; the first circuit layer comprises a first bitline selector, and the second circuit layer comprises a second bitline selector; the first bitline selector is configured to couple one bitline segment selected from among a first set of bitline segments disposed on the first circuit layer to a first conductive through via structure of the conductive through via structures, and the second bitline selector is configured to couple one bitline segment selected from among a second set of bitline segments disposed on the second circuit layer to the first conductive through via structure.
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