US 12,175,947 B2
Display device
Hidetomo Kobayashi, Kanagawa (JP); Kei Takahashi, Kanagawa (JP); and Shunpei Yamazaki, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Apr. 18, 2023, as Appl. No. 18/135,818.
Application 18/135,818 is a continuation of application No. 17/521,100, filed on Nov. 8, 2021, granted, now 11,640,807.
Application 17/521,100 is a continuation of application No. 16/901,129, filed on Jun. 15, 2020, granted, now 11,462,185, issued on Oct. 4, 2022.
Application 16/901,129 is a continuation of application No. 15/866,880, filed on Jan. 10, 2018, granted, now 10,692,452, issued on Jun. 23, 2020.
Claims priority of application No. 2017-005376 (JP), filed on Jan. 16, 2017; and application No. 2017-005407 (JP), filed on Jan. 16, 2017.
Prior Publication US 2023/0260473 A1, Aug. 17, 2023
Int. Cl. G09G 3/36 (2006.01); G02B 27/01 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G06F 1/16 (2006.01); G09G 3/3233 (2016.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H04M 1/02 (2006.01); G02F 1/13 (2006.01); G02F 1/1333 (2006.01); G02F 1/13357 (2006.01); G02F 1/1345 (2006.01); G02F 1/136 (2006.01)
CPC G09G 3/3648 (2013.01) [G02B 27/01 (2013.01); G02F 1/1343 (2013.01); G02F 1/136286 (2013.01); G06F 1/1652 (2013.01); G09G 3/3233 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 29/78648 (2013.01); H04M 1/0268 (2013.01); G02F 1/1303 (2013.01); G02F 1/133391 (2021.01); G02F 1/133602 (2013.01); G02F 1/13452 (2013.01); G02F 1/13458 (2013.01); G02F 1/13606 (2021.01); G02F 2201/52 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0452 (2013.01); G09G 2310/0264 (2013.01); G09G 2320/0223 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A display device comprising:
a display portion, the display portion comprising:
a first pixel electrode;
a first capacitor electrically connected to the first pixel electrode;
a first transistor electrically connected to the first capacitor;
a second pixel electrode;
a second capacitor electrically connected to the second pixel electrode;
a second transistor electrically connected to the second capacitor;
a scan line electrically connected to a gate of the first transistor;
a first signal line electrically connected to the first transistor; and
a second signal line electrically connected to the second transistor,
wherein the scan line has a region extending in a first direction,
wherein the first signal line has a region extending in a second direction intersecting the first direction,
wherein the second signal line has a region extending in the second direction,
wherein the first pixel electrode and the second pixel electrode are provided adjacent to each other in the second direction,
wherein, in a plan view, the first signal line has a region between the first pixel electrode and the second signal line and a region between the second pixel electrode and the second signal line,
wherein the second transistor comprises a semiconductor layer comprising a channel formation region,
wherein the semiconductor layer comprises an oxide semiconductor,
wherein the semiconductor layer does not overlap with the first signal line and the second signal line,
wherein a first conductive layer is configured to electrically connect the semiconductor layer and the second signal line,
wherein the first conductive layer has a region extending in the first direction,
wherein the first conductive layer has a region intersecting the first signal line,
wherein the first conductive layer overlaps with a first opening and a second opening, and
wherein the first opening and the second opening are not aligned in the first direction and the second direction.