US 12,175,917 B1
Gate drive circuit and display panel
Song He, Guangdong (CN); Xiaojin He, Guangdong (CN); Xu Wang, Guangdong (CN); and Zelin Yang, Guangdong (CN)
Assigned to TCL China Star Optoelectronics Technology Co., Ltd., Shenzhen (CN)
Filed by TCL China Star Optoelectronics Technology Co., Ltd., Guangdong (CN)
Filed on Dec. 28, 2023, as Appl. No. 18/398,476.
Claims priority of application No. 202311725764.2 (CN), filed on Dec. 14, 2023.
Int. Cl. G09G 3/3266 (2016.01); G09G 3/20 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 2310/0267 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A gate drive circuit, wherein the gate drive circuit comprises multi-stage cascaded gate drive units, each gate drive unit comprises a pull-up control module, an output module, a pull-down module, a pull-down maintain module, a first reference low-level signal input terminal, a second reference low-level signal input terminal, and a pull-up node located on a line between the pull-up control module and the output module;
the pull-up control module comprises a pull-up control transistor, the pull-up control transistor is electrically connected to the pull-up node, and the pull-up control transistor is configured to pull a potential of the pull-up node up;
the output module comprises a scan signal output transistor, the scan signal output transistor is electrically connected to the pull-up node, the scan signal output transistor is configured to output a present-stage scan signal under control of the potential of the pull-up node;
the pull-down module is electrically connected to the pull-up node, the first reference low-level signal input terminal, and the pull-up maintain module, and the pull-down module is configured to pull the potential of the pull-up node down to a potential of a first reference low-level signal inputted by the first reference low-level signal input terminal;
the pull-down maintain module is electrically connected to the pull-up node and the second reference low-level signal input terminal, the pull-down maintain module is configured to maintain the potential of the pull-up node at a potential of a second reference low-level signal inputted by the second reference low-level signal input terminal; and
wherein a ratio of a channel length of the pull-up control transistor to a channel length of the scan signal output transistor is between 1:8 and 1:12.