US 12,175,274 B2
Process-based multi-key total memory encryption
Wajdi Feghali, Boston, MA (US); Vinodh Gopal, Westborough, MA (US); Kirk S. Yap, Westborough, MA (US); Sean Gulley, Sudbury, MA (US); and Raghunandan Makaram, Northborough, MA (US)
Assigned to Tahoe Research, Ltd., Dublin (IE)
Filed by Tahoe Research, Ltd., Dublin (IE)
Filed on Aug. 26, 2022, as Appl. No. 17/896,510.
Application 17/896,510 is a continuation of application No. 17/127,729, filed on Dec. 18, 2020, granted, now 11,494,222.
Application 17/127,729 is a continuation of application No. 16/145,659, filed on Sep. 28, 2018, granted, now 10,871,983, issued on Dec. 22, 2020.
Claims priority of provisional application 62/678,783, filed on May 31, 2018.
Prior Publication US 2023/0101226 A1, Mar. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/455 (2018.01); G06F 12/14 (2006.01); H04L 9/08 (2006.01)
CPC G06F 9/45558 (2013.01) [G06F 12/1408 (2013.01); G06F 12/1466 (2013.01); G06F 12/1475 (2013.01); H04L 9/0894 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45587 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/402 (2013.01)] 16 Claims
OG exemplary drawing
 
7. A per-process memory encryption system, comprising, in each core of a multi-core processor:
at least one translation lookaside buffer (TLB) configured to map virtual memory addresses to physical addresses, wherein the TLB is configured to encode key identifiers for keys in one or more bits of either a virtual memory address or a physical address in the TLB;
a process state memory configured to store a first process key table for a first process that maps key identifiers to a first set of keys and a second process key table for a second process that maps the key identifiers to a second set of keys different from the first set of keys; and
an active process key table memory configured to selectively store one of the first process key table or the second process key table based on determining which of the first process or the second process is active.