US 12,175,253 B2
Calculating device
Kosuke Tatsumura, Yokohama Kanagawa (JP); and Hayato Goto, Kawasaki Kanagawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP)
Filed on Mar. 21, 2023, as Appl. No. 18/187,514.
Application 18/187,514 is a division of application No. 17/027,744, filed on Sep. 22, 2020, granted, now 11,640,303.
Application 17/027,744 is a division of application No. 16/118,646, filed on Aug. 31, 2018, granted, now 10,817,304, issued on Oct. 27, 2020.
Claims priority of application No. 2018-043217 (JP), filed on Mar. 9, 2018.
Prior Publication US 2023/0221962 A1, Jul. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 7/544 (2006.01); G06F 7/57 (2006.01); G06F 7/72 (2006.01); G06F 9/30 (2018.01)
CPC G06F 9/3893 (2013.01) [G06F 7/5443 (2013.01); G06F 7/57 (2013.01); G06F 7/72 (2013.01); G06F 9/3001 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A calculating device, comprising:
a first chip; and
a second chip,
the first chip including:
a first memory;
a second memory;
a third memory;
a first arithmetic module; and
a second arithmetic module,
the first memory being configured to store a part of a first variable group {x},
the second memory being configured to store a part of a second variable group {y},
the third memory being configured to store a part of a first parameter group {J},
the second chip including:
an other first memory;
an other second memory;
an other third memory;
an other first arithmetic module; and
an other second arithmetic module,
the other first memory being configured to store an other part of the first variable group {x},
the other second memory being configured to store an other part of the second variable group {y},
the other third memory being configured to store an other part of the first parameter group {J},
the first chip being configured to acquire at least a portion of the other part of the first variable group {x} from the second chip,
the second chip being configured to acquire at least a portion of the part of the first variable group {x} from the first chip,
the first arithmetic module being configured to update the part of the first variable group {x} based on the part of the second variable group {y},
the second arithmetic module being configured to update the part of the second variable group {y} based on at least a portion of the part of the first parameter group {J} and at least a portion of the other part of the first variable group {x} acquired from the second chip,
the other first arithmetic module being configured to update the other part of the first variable group {x} based on the other part of the second variable group {y}, and
the other second arithmetic module being configured to update the other part of the second variable group {y} based on at least a portion of the other part of the first parameter group {J} and at least a portion of the part of the first variable group {x} acquired from the first chip.