US 12,175,180 B2
Systems and methods for context aware circuit design
Li-Chung Hsu, Hsin-Chu (TW); Yen-Pin Chen, Taipei (TW); Sung-Yen Yeh, Jiadong Township, Pingtung County (TW); Jerry Chang-Jui Kao, Taipei (TW); and Chung-Hsing Wang, Hinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/232,742.
Application 18/232,742 is a division of application No. 17/370,717, filed on Jul. 8, 2021, granted, now 11,816,413.
Application 17/370,717 is a continuation of application No. 16/836,370, filed on Mar. 31, 2020, granted, now 11,068,637.
Prior Publication US 2023/0401369 A1, Dec. 14, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/392 (2020.01); G06F 30/367 (2020.01); G06F 113/18 (2020.01); G06F 119/06 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/367 (2020.01); G06F 2113/18 (2020.01); G06F 2119/06 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A system for designing a circuit, comprising:
a non-transitory storage medium encoded with a set of instructions; and
a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute the set of instructions, the set of instructions being configured to cause the processor to:
identify a subset of standard cells configured for designing the circuit;
determine at least one key context parameter for cells in the subset, based on a sensitivity of at least one electrical property of the cells to the at least one key context parameter;
generate at least one derate table based on the sensitivity of the at least one electrical property of the cells to the at least one key context parameter; and
perform a static analysis of the circuit based on the at least one derate table.