US 12,175,176 B2
Fast synthesis of logical circuit design with predictive timing
Peter Moceyunas, Los Altos, CA (US); Jiong Luo, Morgan Hill, CA (US); Luca Amaru, Santa Clara, CA (US); Casey The, Cupertino, CA (US); Jovanka Ciric Vujkovic, Mountain View, CA (US); and Patrick Vuillod, St. Bernard du Touve (FR)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Mar. 11, 2022, as Appl. No. 17/693,236.
Claims priority of provisional application 63/162,160, filed on Mar. 17, 2021.
Prior Publication US 2022/0300688 A1, Sep. 22, 2022
Int. Cl. G06F 30/327 (2020.01); G06F 30/323 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 30/323 (2020.01); G06F 2119/12 (2020.01)] 17 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
receiving a logical design of a circuit of an integrated circuit;
applying, by a processor, a reduced synthesis process to the logical design of the circuit, the reduced synthesis process generating a netlist having suboptimal delay through one or more stages of the netlist;
providing the generated netlist as input to a timing prediction delay model that determines delay as a function of timing context of gates and nets of the circuit, wherein the timing prediction delay model determines scale factors used in determining delay based on estimated quality of optimization by the reduced synthesis process of the stages of the generated netlist; and
executing the timing prediction delay model using the scale factors, to determine an estimate of timing for the logical design of the circuit.