US 12,174,769 B2
Periodic receiver clock data recovery with dynamic data edge
Gurunath Dollin, Santa Clara, CA (US); Edoardo Prete, Boxborough, MA (US); Milam Paraschou, Santa Clara, CA (US); Edward Wade Thoenes, Boxborough, MA (US); Ryan J. Hensley, Austin, TX (US); and Gerald R. Talbot, Boxborough, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Mar. 25, 2022, as Appl. No. 17/705,048.
Prior Publication US 2023/0305979 A1, Sep. 28, 2023
Int. Cl. G06F 13/40 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01); G06F 13/42 (2006.01); H03K 19/173 (2006.01)
CPC G06F 13/4022 (2013.01) [G06F 1/08 (2013.01); G06F 1/12 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); H03K 19/1737 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first serial-to-parallel conversion circuit and a second serial-to-parallel conversion circuit; and
a control circuit configured to:
responsive to a calibration routine being initiated, cause the first serial-to-parallel conversion circuit to output data using a first data path and the second serial-to-parallel conversion circuit to output data using a second data path different from the first data path; and
responsive to the calibration routine being completed, cause the first serial-to-parallel conversion circuit to output data using the second data path and the second serial-to-parallel conversion circuit to output data using the first data path.