US 12,174,753 B2
Methods and apparatus for transferring data within hierarchical cache circuitry
Joseph Michael Pusdesris, Austin, TX (US); Klas Magnus Bruce, Austin, TX (US); Jamshed Jalal, Austin, TX (US); Dimitrios Kaseridis, Austin, TX (US); Gurunath Ramagiri, Austin, TX (US); Ho-Seop Kim, Austin, TX (US); Andrew John Turner, Cambridge (GB); and Rania Hussein Hassan Mameesh, Cambridge (GB)
Assigned to Arm Limited, Cambridge (GB)
Appl. No. 18/253,621
Filed by Arm Limited, Cambridge (GB)
PCT Filed Nov. 18, 2021, PCT No. PCT/EP2021/082196
§ 371(c)(1), (2) Date May 19, 2023,
PCT Pub. No. WO2022/112099, PCT Pub. Date Jun. 2, 2022.
Claims priority of application No. 20386053 (EP), filed on Nov. 25, 2020.
Prior Publication US 2023/0418766 A1, Dec. 28, 2023
Int. Cl. G06F 12/126 (2016.01); G06F 12/0811 (2016.01)
CPC G06F 12/126 (2013.01) [G06F 12/0811 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus comprising:
processing circuitry configured to issue access requests in respect of data;
first cache circuitry for storing temporary copies of data from a memory, for providing to the processing circuitry in response to corresponding access requests; second cache circuitry for storing temporary copies of data from the memory, for providing to the first cache circuitry in response to corresponding access requests, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry, wherein:
the second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to:
identify said data as pseudo-invalid data; and,
provide said data to the first cache circuitry, the second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to:
responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.