US 12,174,747 B2
Last level cache access during non-Cstate self refresh
Benjamin Tsien, Fremont, CA (US); Chintan S. Patel, San Antonio, TX (US); Guhan Krishnan, Acton, MA (US); Andrew William Lueck, Austin, TX (US); and Sreenath Thangarajan, Chennai (IN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,617.
Prior Publication US 2023/0195644 A1, Jun. 22, 2023
Int. Cl. G06F 12/0897 (2016.01)
CPC G06F 12/0897 (2013.01) [G06F 2212/60 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A data processor comprising:
a data fabric for routing requests between a plurality of requestors and a plurality of responders;
a memory controller for accessing a volatile memory;
a last level cache coupled between the memory controller and the data fabric and including a cache memory separate from the volatile memory; and
a traffic monitor coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller to and from the volatile memory, and based on detecting an idle condition in the monitored traffic, cause the memory controller to command the volatile memory to enter self-refresh mode, wherein the traffic monitor is further operable to cause the memory controller to enter a selected C-state based on detecting the idle condition, the selected C-state including the data fabric and last level cache maintaining an operational power state.