US 12,174,254 B2
Fault detection method and related apparatus
Zhe Tao, Shanghai (CN); Ge Shen, Shenzhen (CN); Jianlong Cao, Shanghai (CN); Ming Wang, Shenzhen (CN); and Rui Fang, Shanghai (CN)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed on Apr. 27, 2023, as Appl. No. 18/308,405.
Application 18/308,405 is a continuation of application No. PCT/CN2021/126873, filed on Oct. 28, 2021.
Claims priority of application No. 202011180288.7 (CN), filed on Oct. 29, 2020.
Prior Publication US 2023/0258718 A1, Aug. 17, 2023
Int. Cl. G01R 31/3185 (2006.01); G06F 9/48 (2006.01)
CPC G01R 31/318544 (2013.01) [G06F 9/4881 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A fault detection method comprising:
obtaining a scheduling table of a target task, wherein the scheduling table indicates test patterns and an execution sequence of a first test pattern, wherein the test patterns comprise the first test pattern, wherein the first test pattern is for detecting a fault in a target logic circuit, wherein the target logic circuit is for executing the target task, and wherein the execution sequence is based on a quantity of execution times of an instruction type; and
executing the first test pattern based on the scheduling table to detect the fault.