US RE49,770 E1
Flexible display having a crack suppressing layer
Kwang-Nyun Kim, Yongin (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Apr. 27, 2021, as Appl. No. 17/241,197.
Application 14/300,765 is a continuation of application No. 16/163,753, filed on Oct. 18, 2018, granted, now RE48540.
Application 17/241,197 is a reissue of application No. 14/300,765, filed on Jun. 10, 2014, granted, now 9,472,779, issued on Oct. 18, 2016.
Application 16/163,753 is a reissue of application No. 14/300,765, filed on Jun. 10, 2014, granted, now 9,472,779, issued on Oct. 18, 2016.
Claims priority of application No. 10-2013-0096161 (KR), filed on Aug. 13, 2013.
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 51/42 (2006.01); H01L 27/32 (2006.01); H01L 51/56 (2006.01); H01L 51/00 (2006.01); H10K 50/844 (2023.01); H10K 77/10 (2023.01); H10K 59/80 (2023.01); H10K 50/84 (2023.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01); H10K 59/122 (2023.01); H10K 102/00 (2023.01); H10K 59/124 (2023.01)
CPC H10K 50/844 (2023.02) [H10K 50/841 (2023.02); H10K 59/12 (2023.02); H10K 59/8722 (2023.02); H10K 71/00 (2023.02); H10K 77/111 (2023.02); H10K 59/122 (2023.02); H10K 59/124 (2023.02); H10K 59/873 (2023.02); H10K 71/851 (2023.02); H10K 2102/311 (2023.02); Y02E 10/549 (2013.01); Y02P 70/50 (2015.11)] 20 Claims
OG exemplary drawing
 
[ 18. A flexible display, comprising:
a flexible substrate;
a transistor disposed on the flexible substrate and including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode;
a plurality of inorganic layers including a barrier layer, a buffer layer, a gate insulating layer, and an interlayer insulating layer sequentially disposed on the flexible substrate;
a light emitting element disposed on the interlayer insulating layer and electrically connected to the transistor;
a thin film encapsulation layer covering the light emitting element; and
a crack suppressing layer disposed directly on the interlayer insulating layer and along an edge of the flexible substrate,
wherein at least one of the barrier layer and the buffer layer is disposed at the edge of the flexible substrate,
wherein at least one of an edge of the gate insulating layer and an edge of the interlayer insulating layer is spaced apart from the edge of the flexible substrate. ]